CD4027BE CD4027 CD-4027 4027 DIP-16 Pin Package CMOS Dual J-K Master-Slave Flip-Flop Breadboard Friendly IC

CD4027 dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive- going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS.

What is a JK Flip-Flop?

The JK Flip Flop is basically a gated RS flip flop with the addition of the clock input circuitry. When both the inputs S and R are equal to logic “1”, the invalid condition takes place. Thus to prevent this invalid condition, a clock circuit is introduced. The JK Flip Flop has four possible input combinations because of the addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”. “No change’ and “Toggle”.

CD4027 Key Features

• Wide supply voltage range 3.0V to 15V
• High noise immunity 0.45 VDD (typ.)
• Low power TTL compatibility Fan out of 2 driving 74L or 1 driving 74LS
• Low power 50 nW (typ.)
• Medium speed operation 12 MHz (typ.) with 10V supply

CD4027 Pinout

Application

• Shift Registers
• Ripple Binary Counters

Package Include:

• 1 x CD4027 IC CD 4027 DIP 16 Pin IC